The present invention relates generally to the configuration of programmable logic in a configurable system on a chip, and more specifically to a system and method for the configuration, reconfiguration, and readback of a portion of the programmable logic array.
A recent development in microelectronics is the configurable system on a chip (CSoC). FIG. 1 is a block diagram of a configurable system on a chip. The system 100 shown in FIG. 1 includes those portions of a CSoC relevant to an embodiment of the present invention. The system integrates a CPU 105, an internal system bus 110, configuration logic 115 and programmable logic, also referred to as configurable system logic (CSL) 120. The various system resources are all interconnected, and communicating through the internal system bus 110, on a single piece of silicon. The internal system bus signals and various dedicated system resource signals that connect to the CSL 120 are collectively referred to as the configurable system interconnect or CSI 110. The CSL consists of a plane of configuration memory cells that typically could be static random access memory (SRAM) coupled to user logic. The memory cells are configured to a known value prior to the operation of the device. This configuration determines the behavior of the logic and allows a programmer to implement desired functionality. For example a user may implement basic logic functions such as counters, adders, and multipliers, or more complex digital logic systems such as universal asynchronous receiver transmitters (UARTs). Since the configuration memory space of a CSoC is randomly accessible as part of the CSI address space no other dedicated hardware is necessary to configure the configurable memory of CSL 120. The CPU 105 simply writes the configuration data to the appropriate configuration memory location.
A user may wish to reconfigure a portion of the user logic to provide a different functionality. For example, a user may wish to reconfigure a UART as something else or simply change the baud rate or the parity bit of the UART. To do this the entire CSL is deactivated, the reconfiguration is completed, and the CSL is reactivated. During the time the CSL is deactivated, none of the functionality implemented through the user logic is available.
FIG. 2 shows CSL 120 as discussed above in reference to FIG. 1. CSL 120 includes an array 201 of configuration memory cells that could be, for example, SRAM cells. The array of SRAM cells 201 could be single bits or alternatively could be 8 bit words or 32 bit words depending on bus length. Typically a SRAM based configuration memory array may contain hundreds of thousands of memory cells. Shown coupled to CSL 120 is configuration logic that includes row select circuitry 202 and column select circuitry 204, as well as other configuration circuitry 206. Typically, SRAM based configuration memory is configured a row or column at a time. Each bit, or word, may have to be sequentially accessed in order to write information into the memory cells. To configure or reconfigure any part of the device, the entire row or column of SRAM cells may be altered. The access time is increased because the entire row and column designating the configuration memory cells to be configured must be selected. Configuration by row and column may also interfere with surrounding logic. This can be avoided by insulating the surrounding logic, but this is cost prohibitive. Also, large arrays necessitate lengthy select lines and data lines. The longer lines degrade reliability. In a system, such as the CSoC, in which a processor, system bus, and programmable logic are all tightly coupled together, functions in the programmable logic are typically grouped into blocks. This makes the row/column configuration method even more inefficient.
A method and system are described for configuring the programmable logic of a configurable system on a chip. The array of system addressable configuration memory cells is partitioned into a plurality of banks. Configuration circuitry is implemented for each bank. While one or more of the banks is configured the other banks remain operable.